Automatic testbench in VHDL
Verification is a really important field in circuit design, but writing good testcases can be both cumbersome and a big challenge. Because it is often needed to test a large amount of different cases, some sort of automatic testbench is valuable.
This software is written in Python and VHDL and was a part of a project in the class "TFE4175 Realization and test of digital components". This was an interesting project were we designed a circuit for encrypting data using the RSA-algorithm. We simulated, verificated and synthesized the circuit from a VHDL description.
The actual testbench is written in VHDL and takes two sample files generated by Python scripts. input_module.dat contains input values which will be used to stimulate the circuit, while output_module.dat contains expected output which the output of the circuit will be checked against. As usual, values equal 'X' means don't care and will be ignored.
To find the expected output and which input values to stimulate in input_module.dat and output_module.dat, you can write a description of your circuit in for example Python. The provided code shows an example of how this could be done.
The cool thing about this testbench is that you can write a complete description of your circuit in a software language like for example Python or C++. The concept of writing multiple functionally equivalent programs is called N-version programming and the advantages can be quite large.
